This invention relates generally to digital electronic equipment, and more particularly to methods and apparatus for reducing power consumption for personal computer systems.
The electronics industry continues to strive for high-powered, high-functioning circuits. Significant achievements in this regard have been realized through the fabrication of very large-scale integration of circuits on small areas of silicon wafer. Integrated circuits of this type are developed through a series of steps carried out in a particular order. Main goals in designing such devices include realizing a device that operates at high speeds while consuming relatively small amounts of power.
There are variety of reasons why computer designers wish to reduce power consumption in personal computers. Portable computers, for example, typically depend on batteries for power; the less power consumed by the portable computer circuitry and peripherals, the longer the batteries will last. In addition to portable computer applications, it is also often desirable to have stationary (e.g., desktop) computers that consume less power. This is because reduced power consumption reduces energy costs and, in a cumulative sense, reduces the negative environmental impacts of excessive energy consumption. Furthermore, desktop computers designed to consume less power also generate less heat, which means that they can be made smaller and with reduced cooling requirements.
Previous approaches have been used to reduce power consumption in such devices. One approach, for example, is to shut down peripherals or very large functional system blocks that have not been used for a predetermined period of time. Another known technique reduces computer power consumption by reducing the speed of the clock driving the digital circuitry. Since there is a direct relationship between clock rate and power consumption, any lowering of the clock rate will typically reduce power consumption.
Semiconductor devices are used in large numbers to construct most modern electronic devices. In order to increase the capability of such electronic devices, it is necessary to integrate even larger numbers of such devices into a single silicon wafer. As the semiconductor devices are scaled down (i.e., made smaller) to form a larger number of devices on a given surface area, the structure of the devices and the fabrication techniques used to make such devices have become more refined. This increased ability to refine such semiconductor devices has lead to an ever-increasing proliferation of customized chips and, for many applications, each chip is typically driven by one or more operational clocks for communication on a common data bus. In these common bus applications, attempting to manage power consumed by each of these chips is burdened by a number of delays resulting from transitioning a power-reduced chip or block to fully-operational mode.
Accordingly, there is a need for a way to manage power consumption to communicatively-coupled chips or functional blocks in a manner that is efficient and consistent with the ideal of realizing a device that operates at high speeds while consuming relatively small amounts of power.
The present invention is directed to addressing the above need by way of a power-efficient multi-block data processing arrangement that permits transition of a power-reduced chip or block to fully-operational mode in a manner that is transparent to an access of the power-reduced chip or block.
According to one embodiment, a power management system permits power-reduced operation of selected circuit blocks in a manner that is transparent to other bus-coupled circuit blocks. Consistent with one embodiment of the present invention, the approach is implemented in a digital electronic circuit arrangement having an accessing circuit block coupled to a clocked circuit block over a data bus. The clocked circuit block is power managed by decreasing, e.g., reducing or blocking, the clock speed to the clocked circuit block which impedes its ability communicate over the data bus. Once the clocked circuit block is set in a reduced power mode, the bus is monitored for data-access communications from the accessing circuit block to the clocked circuit block. In response to such a communication, a substitute response is generated on the data bus, directed to the accessing circuit block, and the clock speed to the clocked circuit block is increased and brought out of the reduced power mode for further communications with the accessing circuit block. The substitute response is presented during a clock period during which the clocked circuit block would respond when in a mode other than the reduced power mode.
Other aspects of the present invention are directed and related to circuit arrangements and methods using the above approach or variations thereof.